Table Name |
Stage Number |
Crossbar Bytes |
Hash Bits |
Gateways |
RAMs |
TCAMs |
Map RAMs |
Action Data Bus Bytes |
VLIW Slots |
Exm Search Bus |
Exm Result Bus |
Tind Result Bus |
_condition_0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
_condition_2 |
0 |
1 |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
ipv4_lpm__action__ |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
ipv4_lpm |
0 |
4 |
0 |
0 |
1 |
1 |
0 |
0 |
2 |
0 |
0 |
1 |
int_set_header_2_tbl__action__ |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
int_set_header_2_tbl |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
_condition_1 |
1 |
1 |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
int_set_intl45_head_header_tbl__action__ |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
int_set_intl45_head_header_tbl |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |