Table Name |
Stage Number |
Crossbar Bytes |
Hash Bits |
Gateways |
RAMs |
TCAMs |
Map RAMs |
Action Data Bus Bytes |
VLIW Slots |
Exm Search Bus |
Exm Result Bus |
Tind Result Bus |
_condition_0 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
_condition_1 |
0 |
2 |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
update_srcip_dstip_tbl__action__ |
0 |
13 |
13 |
0 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
update_srcip_dstip_tbl |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
update_srcport_dstport_tbl__action__ |
0 |
13 |
13 |
0 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
update_srcport_dstport_tbl |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
update_protocol_tbl__action__ |
0 |
13 |
13 |
0 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
update_protocol_tbl |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
ipv4_lpm__action__ |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
ipv4_lpm |
0 |
4 |
0 |
0 |
1 |
1 |
0 |
0 |
2 |
0 |
0 |
1 |
set_egmeta_tbl__action__ |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
set_egmeta_tbl |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
int_srcip_dstip_reg |
0 |
8 |
32 |
0 |
5 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
int_srcport_dstport_reg |
0 |
4 |
0 |
0 |
3 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
int_protocol_reg |
0 |
1 |
0 |
0 |
2 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
_condition_2 |
1 |
2 |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
update_latency_tbl__action__ |
1 |
13 |
13 |
0 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
update_latency_tbl |
1 |
3 |
30 |
0 |
3 |
0 |
0 |
0 |
3 |
1 |
1 |
0 |
int_latency_reg |
1 |
4 |
0 |
0 |
5 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
_condition_3 |
2 |
2 |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
latency_insert_tbl__action__ |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
latency_insert_tbl |
2 |
7 |
30 |
0 |
3 |
0 |
0 |
0 |
2 |
1 |
1 |
0 |