Row 255

State <POV initialization>_<Ingress intrinsic metadata> (from state <Shim start state>)

[.] Raw register data



[.] Input buffer

Matches   
8[0]
Bytes   
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Extractions   
65
67
 
8-bit extracts: 2
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

8b[0]  
00 && 80  -> Row 235 (state <Phase 0>)


Row 254

State parse_udp (from state parse_ipv4)

[.] Raw register data



[.] Input buffer

Matches   
16
Bytes   
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Extractions   
2
264
 
PHV 129 |= 0x4

8-bit extracts: 0
16-bit extracts: 1
32-bit extracts: 2



[.] Transitions

16b  
04d2  -> Row 252 (state parse_int_prepare)
Default  -> Row 251 (state <leaf>)

Previous states: Row 234


Row 253

State <leaf> (from state parse_ipv4)

[.] Raw register data



[.] Input buffer

Matches   
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Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

End

Previous states: Row 234


Row 252

State parse_int_prepare (from state parse_udp)

[.] Raw register data



[.] Saved matches

8b[0] <- Row 234


[.] Input buffer

Matches   
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Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

8b[0]  
00 && 01  -> Row 250 (state <leaf>)
01 && 01  -> Row 249 (state parse_int)
Default  -> Row 248 (state <leaf>)

Previous states: Row 254


Row 251

State <leaf> (from state parse_udp)

[.] Raw register data



[.] Input buffer

Matches   
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31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

End

Previous states: Row 254


Row 250

State <leaf> (from state parse_int_prepare)

[.] Raw register data



[.] Input buffer

Matches   
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0
1
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8
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27
28
29
30
31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

End

Previous states: Row 252


Row 249

State parse_int (from state parse_int_prepare)

[.] Raw register data



[.] Input buffer

Matches   
8[0]
8[1]
16
Bytes   
0
1
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25
26
27
28
29
30
31
Extractions   
69
 
PHV 129 |= 0x8

8-bit extracts: 1
16-bit extracts: 1
32-bit extracts: 0



[.] Transitions

 
Default  -> Row 247 (state parse_deviceid)
Default  -> Row 246 (state check_iport)

Previous states: Row 252


Row 248

State <leaf> (from state parse_int_prepare)

[.] Raw register data



[.] Input buffer

Matches   
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0
1
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8
9
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21
22
23
24
25
26
27
28
29
30
31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

End

Previous states: Row 252


Row 247

State parse_deviceid (from state parse_int)

[.] Raw register data



[.] Input buffer

Matches   
Bytes   
0
1
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3
4
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8
9
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25
26
27
28
29
30
31
Extractions   
70
 
PHV 129 |= 0x10

8-bit extracts: 1
16-bit extracts: 1
32-bit extracts: 0



[.] Transitions

 
Default  -> Row 245 (state check_iport)

Previous states: Row 249


Row 246

State check_iport (from state parse_int)

[.] Raw register data



[.] Saved matches

8b[0] <- Row 249


[.] Input buffer

Matches   
Bytes   
0
1
2
3
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8
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23
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25
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31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

8b[0]  
40 && 40  -> Row 244 (state parse_iport)
Default  -> Row 243 (state check_eport)

Previous states: Row 249


Row 245

State check_iport (from state parse_deviceid)

[.] Raw register data



[.] Saved matches

8b[0] <- Row 249


[.] Input buffer

Matches   
Bytes   
0
1
2
3
4
5
6
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8
9
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14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

8b[0]  
40 && 40  -> Row 244 (state parse_iport)
Default  -> Row 243 (state check_eport)

Previous states: Row 247


Row 244

State parse_iport (from state check_iport)

[.] Raw register data



[.] Input buffer

Matches   
Bytes   
0
1
2
3
4
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6
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8
9
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24
25
26
27
28
29
30
31
Extractions   
66
 
PHV 129 |= 0x20

8-bit extracts: 1
16-bit extracts: 1
32-bit extracts: 0



[.] Transitions

 
Default  -> Row 242 (state check_eport)

Previous states: Row 245, Row 246


Row 243

State check_eport (from state check_iport)

[.] Raw register data



[.] Saved matches

8b[1] <- Row 249


[.] Input buffer

Matches   
Bytes   
0
1
2
3
4
5
6
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8
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23
24
25
26
27
28
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31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

8b[1]  
20 && 20  -> Row 241 (state parse_eport)
Default  -> Row 240 (state check_latency)

Previous states: Row 245, Row 246


Row 242

State check_eport (from state parse_iport)

[.] Raw register data



[.] Saved matches

8b[1] <- Row 249


[.] Input buffer

Matches   
Bytes   
0
1
2
3
4
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8
9
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15
16
17
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20
21
22
23
24
25
26
27
28
29
30
31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

8b[1]  
20 && 20  -> Row 241 (state parse_eport)
Default  -> Row 240 (state check_latency)

Previous states: Row 244


Row 241

State parse_eport (from state check_eport)

[.] Raw register data



[.] Input buffer

Matches   
Bytes   
0
1
2
3
4
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6
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8
9
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25
26
27
28
29
30
31
Extractions   
71
 
PHV 129 |= 0x40

8-bit extracts: 1
16-bit extracts: 1
32-bit extracts: 0



[.] Transitions

 
Default  -> Row 239 (state check_latency)

Previous states: Row 242, Row 243


Row 240

State check_latency (from state check_eport)

[.] Raw register data





[.] Input buffer

Matches   
Bytes   
0
1
2
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8
9
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25
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28
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31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

16b  
1000 && 1000  -> Row 238 (state parse_latency)
Default  -> Row 237 (state <leaf>)

Previous states: Row 242, Row 243


Row 239

State check_latency (from state parse_eport)

[.] Raw register data





[.] Input buffer

Matches   
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0
1
2
3
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8
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31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

16b  
1000 && 1000  -> Row 238 (state parse_latency)
Default  -> Row 237 (state <leaf>)

Previous states: Row 241


Row 238

State parse_latency (from state check_latency)

[.] Raw register data



[.] Input buffer

Matches   
Bytes   
0
1
2
3
4
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6
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8
9
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27
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31
Extractions   
3
 
PHV 129 |= 0x80

8-bit extracts: 0
16-bit extracts: 1
32-bit extracts: 1



[.] Transitions

End

Previous states: Row 240, Row 239


Row 237

State <leaf> (from state check_latency)

[.] Raw register data



[.] Input buffer

Matches   
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1
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8
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31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

End

Previous states: Row 240, Row 239


Row 236

State start_parse_ethernet (from state <Phase 0>)

[.] Raw register data



[.] Input buffer

Matches   
16
Bytes   
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27
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29
30
31
Extractions   
289
258
322
290
259
323
 
PHV 129 |= 0x100

PHV 129 |= 0x1

8-bit extracts: 2
16-bit extracts: 4
32-bit extracts: 2



[.] Transitions

16b  
0800  -> Row 234 (state parse_ipv4)
Default  -> Row 233 (state <leaf>)

Previous states: Row 235


Row 235

State <Phase 0> (from state <POV initialization>_<Ingress intrinsic metadata>)

[.] Raw register data



[.] Input buffer

Matches   
8[0]
Bytes   
0
1
2
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8
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19
20
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22
23
24
25
26
27
28
29
30
31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

 
Default  -> Row 236 (state start_parse_ethernet)

Previous states: Row 255


Row 234

State parse_ipv4 (from state start_parse_ethernet)

[.] Raw register data



[.] Input buffer

Matches   
8[0]
8[1]
Bytes   
0
1
2
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31
Extractions   
320
321
256
68
288
257
1
128
 
PHV 129 |= 0x2

8-bit extracts: 2
16-bit extracts: 4
32-bit extracts: 3



[.] Transitions

8b[1]  
11  -> Row 254 (state parse_udp)
Default  -> Row 253 (state <leaf>)

Previous states: Row 236


Row 233

State <leaf> (from state start_parse_ethernet)

[.] Raw register data



[.] Input buffer

Matches   
Bytes   
0
1
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25
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27
28
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30
31
Extractions   
 
8-bit extracts: 0
16-bit extracts: 0
32-bit extracts: 0



[.] Transitions

End

Previous states: Row 236


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Matchable row occupancy: 23/256 (8.98%)

Created on Fri Aug 5 07:40:16 2022
Compiler version: 5.16.0 (a35e94c)
Run ID: d0aea193bedd5f85