Row 255
State <POV initialization>_<Egress intrinsic metadata> (from state <Shim start state>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
0 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
8 |
38 |
0 |
0 |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
9 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
ad |
0 |
a9 |
aa |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
5f |
62 |
0 |
0 |
1 |
1 |
3 |
0 |
0 |
6 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
1f |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
5 |
2 |
0 |
0 |
|
Row 254
State parse_snap_header (from state parse_llc_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1 |
aaaa |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
5 |
2 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
3 |
0 |
5 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
15e |
15f |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
121 |
1ff |
0 |
0 |
1 |
1 |
3 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
49 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 253
State parse_set_prio_med (from state parse_llc_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1 |
fefe |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 252
State <leaf> (from state parse_llc_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 251
State parse_vlan (from state parse_snap_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
8100 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
3 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
92 |
b2 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
2 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 250
State parse_qinq (from state parse_snap_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
88a8 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
2d |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
92 |
b2 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
2 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 249
State parse_mpls__it0 (from state parse_snap_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
8847 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
4 |
0 |
0 |
2 |
1 |
0 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
c7 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
59 |
70 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 248
State parse_ipv4 (from state parse_snap_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
800 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
12 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 247
State parse_ipv6 (from state parse_snap_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
86dd |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
1ff |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
c |
16 |
0 |
61 |
0 |
0 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 246
State parse_arp_rarp (from state parse_snap_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
806 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
29 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 245
State parse_set_prio_high (from state parse_snap_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
88cc |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 244
State parse_set_prio_high (from state parse_snap_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
8809 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 243
State <leaf> (from state parse_snap_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 242
State parse_mpls__it0 (from state parse_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
8847 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
4 |
0 |
0 |
2 |
1 |
0 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
c7 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
59 |
70 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 241
State parse_ipv4 (from state parse_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
800 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
12 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 240
State parse_ipv6 (from state parse_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
86dd |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
1ff |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
c |
16 |
0 |
61 |
0 |
0 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 239
State parse_arp_rarp (from state parse_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
806 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
29 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 238
State parse_set_prio_high (from state parse_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
88cc |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 237
State parse_set_prio_high (from state parse_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
8809 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 236
State <leaf> (from state parse_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 235
State parse_mpls__it1 (from state parse_mpls__it0)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
4 |
ffff |
ff |
fe |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
5 |
0 |
0 |
2 |
1 |
0 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
c8 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
5b |
71 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 234
State parse_mpls_bos (from state parse_mpls__it0)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
4 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 233
State <leaf> (from state parse_mpls__it0)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
4 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 232
State parse_mpls__it2 (from state parse_mpls__it1)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
5 |
ffff |
ff |
fe |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
6 |
0 |
0 |
2 |
1 |
0 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
c9 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
53 |
73 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 231
State parse_mpls_bos (from state parse_mpls__it1)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
5 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 230
State <leaf> (from state parse_mpls__it1)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
5 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 229
State loop_[p4_parse_state.parse_mpls]_oob (from state parse_mpls__it2)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
6 |
ffff |
ff |
fe |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 228
State parse_mpls_bos (from state parse_mpls__it2)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
6 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 227
State <leaf> (from state parse_mpls__it2)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
6 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 226
State parse_mpls_inner_ipv4 (from state parse_mpls_bos)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
8 |
ffff |
ff |
4f |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
f0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 225
State parse_mpls_inner_ipv6 (from state parse_mpls_bos)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
8 |
ffff |
ff |
6f |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
f0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
e |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 224
State parse_eompls (from state parse_mpls_bos)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
8 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 223
State parse_inner_ipv4 (from state parse_mpls_inner_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
9 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
a |
9 |
0 |
0 |
1 |
1 |
1 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
a7 |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
10 |
17 |
4 |
9 |
0 |
0 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 222
State parse_inner_icmp (from state parse_inner_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
a |
e000 |
1 |
f5 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
ff |
f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
1ff |
1ff |
34 |
0 |
0 |
0 |
0 |
1ff |
1ff |
77 |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
|
Row 221
State parse_inner_tcp (from state parse_inner_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
a |
e000 |
6 |
f5 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
ff |
f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b1 |
0 |
a4 |
ac |
34 |
0 |
0 |
0 |
0 |
57 |
1ff |
77 |
54 |
0 |
0 |
1 |
0 |
6 |
4 |
0 |
2 |
1ff |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
35 |
0 |
36 |
c |
8 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
10 |
0 |
1 |
|
Row 220
State parse_inner_udp (from state parse_inner_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
a |
e000 |
11 |
f5 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
ff |
f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b1 |
0 |
a4 |
ac |
1ff |
0 |
0 |
0 |
0 |
57 |
1ff |
77 |
54 |
0 |
0 |
1 |
0 |
2 |
4 |
0 |
6 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
1 |
|
Row 219
State <leaf> (from state parse_inner_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
a |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 218
State parse_inner_ipv6 (from state parse_mpls_inner_ipv6)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
e |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
f |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
1ff |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
c |
17 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 217
State parse_inner_ipv6//spilled (from state parse_inner_ipv6)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
f |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
1e |
3c |
0 |
0 |
6 |
1 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1b |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1d |
0 |
1f |
14 |
10 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 216
State parse_inner_ethernet (from state parse_eompls)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
10 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
11 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b5 |
b7 |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
64 |
66 |
0 |
0 |
1 |
1 |
0 |
c |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
31 |
0 |
33 |
2 |
19 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
0 |
|
Row 215
State parse_inner_ipv4 (from state parse_inner_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
11 |
800 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
a |
9 |
0 |
0 |
1 |
1 |
1 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
a7 |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
10 |
17 |
4 |
9 |
0 |
0 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 214
State parse_inner_ipv6 (from state parse_inner_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
11 |
86dd |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
f |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
1ff |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
c |
17 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 213
State <leaf> (from state parse_inner_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
11 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 212
State parse_ipv4_no_options (from state parse_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
12 |
c000 |
ff |
f5 |
1 |
1 |
1 |
1 |
mask |
ff |
3fff |
0 |
f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
13 |
0 |
0 |
9 |
1 |
1 |
0 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
a6 |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
10 |
16 |
4 |
51 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 211
State parse_ipv4_option_32b (from state parse_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
12 |
c000 |
ff |
f6 |
1 |
1 |
1 |
1 |
mask |
ff |
3fff |
0 |
f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
a6 |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
10 |
16 |
4 |
51 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 210
State parse_ipv4_other (from state parse_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
12 |
c000 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
3fff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
a6 |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
10 |
16 |
4 |
51 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 209
State parse_ipv4_fragmented_first_pkt (from state parse_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
12 |
e000 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
3fff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
25 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 208
State parse_ipv4_fragmented_other_pkt (from state parse_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
12 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
26 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 207
State parse_icmp (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
1 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
14 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
1ff |
1ff |
31 |
0 |
0 |
0 |
0 |
1ff |
1ff |
77 |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
|
Row 206
State parse_tcp (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
6 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
16 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b0 |
0 |
a5 |
a7 |
31 |
0 |
0 |
0 |
0 |
5c |
1ff |
77 |
5a |
0 |
0 |
1 |
0 |
6 |
4 |
0 |
2 |
1ff |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
33 |
0 |
34 |
c |
8 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
2 |
0 |
1 |
|
Row 205
State parse_udp (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
11 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
8 |
17 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b0 |
0 |
a3 |
ab |
1ff |
0 |
0 |
0 |
0 |
56 |
1ff |
77 |
53 |
0 |
0 |
1 |
0 |
2 |
4 |
0 |
6 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
1 |
|
Row 204
State parse_gre (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
2f |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
1b |
3 |
0 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b0 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
56 |
71 |
0 |
0 |
1 |
1 |
0 |
2 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
71 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
|
Row 203
State parse_ipv4_in_ip (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
4 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 202
State parse_ipv6_in_ip (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
29 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 201
State parse_igmp (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
2 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
18 |
0 |
1ff |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 200
State parse_set_prio_med (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
58 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 199
State parse_set_prio_med (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
59 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 198
State parse_set_prio_med (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
67 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 197
State parse_set_prio_med (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
e000 |
ff |
70 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 196
State <leaf> (from state parse_ipv4_no_options)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
13 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 195
State parse_set_prio_med (from state parse_icmp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
14 |
83ff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
fe00 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 194
State parse_set_prio_med (from state parse_icmp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
14 |
87ff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
fc00 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 193
State parse_set_prio_med (from state parse_icmp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
14 |
88ff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ff00 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 192
State <leaf> (from state parse_icmp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
14 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 191
State parse_set_prio_med (from state parse_tcp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
16 |
b3 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 190
State parse_set_prio_med (from state parse_tcp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
16 |
27f |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 189
State <leaf> (from state parse_tcp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
16 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 188
State parse_vxlan (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
8 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
9a |
1ff |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
70 |
71 |
0 |
0 |
1 |
1 |
0 |
5 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
12 |
0 |
1ff |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
4 |
0 |
0 |
|
Row 187
State parse_geneve (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
17c1 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
8 |
19 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
2 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
9a |
1ff |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
70 |
71 |
0 |
0 |
1 |
1 |
0 |
5 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
12 |
0 |
1ff |
0 |
49 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
4 |
0 |
0 |
|
Row 186
State parse_set_prio_med (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
43 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 185
State parse_set_prio_med (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
44 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 184
State parse_set_prio_med (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
222 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 183
State parse_set_prio_med (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
223 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 182
State parse_set_prio_med (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
208 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 181
State parse_set_prio_med (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
209 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 180
State parse_set_prio_med (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
7c1 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 179
State parse_sflow (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
18c7 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 178
State <leaf> (from state parse_udp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
17 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 177
State parse_inner_ethernet (from state parse_vxlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
18 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
11 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b5 |
b7 |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
64 |
66 |
0 |
0 |
1 |
1 |
0 |
c |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
31 |
0 |
33 |
2 |
19 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
0 |
|
Row 176
State parse_inner_ethernet (from state parse_geneve)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
19 |
6558 |
ff |
0 |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
11 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b5 |
b7 |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
64 |
66 |
0 |
0 |
1 |
1 |
0 |
c |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
31 |
0 |
33 |
2 |
19 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
0 |
|
Row 175
State parse_inner_ipv4 (from state parse_geneve)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
19 |
800 |
ff |
0 |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
a |
9 |
0 |
0 |
1 |
1 |
1 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
a7 |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
10 |
17 |
4 |
9 |
0 |
0 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 174
State parse_inner_ipv6 (from state parse_geneve)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
19 |
86dd |
ff |
0 |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
f |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
1ff |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
c |
17 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 173
State <leaf> (from state parse_geneve)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
19 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 172
State parse_nvgre (from state parse_gre)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1b |
2000 |
58 |
65 |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
ff |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
1c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
9a |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
53 |
70 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
79 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 171
State parse_gre_ipv4 (from state parse_gre)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1b |
0 |
0 |
8 |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
ff |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 170
State parse_gre_ipv6 (from state parse_gre)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1b |
0 |
dd |
86 |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
ff |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
1e |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 169
State parse_erspan_t3 (from state parse_gre)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1b |
0 |
eb |
22 |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
ff |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
c |
1f |
b |
0 |
a |
1 |
1 |
1 |
0 |
8 |
0 |
c |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
ab |
0 |
9a |
a3 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
53 |
70 |
0 |
0 |
1 |
1 |
a |
2 |
0 |
8 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
12 |
0 |
1ff |
4 |
81 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
|
Row 168
State <leaf> (from state parse_gre)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1b |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 167
State parse_inner_ethernet (from state parse_nvgre)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1c |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
11 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b5 |
b7 |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
64 |
66 |
0 |
0 |
1 |
1 |
0 |
c |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
31 |
0 |
33 |
2 |
19 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
0 |
|
Row 166
State parse_inner_ipv4 (from state parse_gre_ipv4)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1d |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
a |
9 |
0 |
0 |
1 |
1 |
1 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
a7 |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
10 |
17 |
4 |
9 |
0 |
0 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 165
State parse_inner_ipv6 (from state parse_gre_ipv6)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1e |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
f |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
1ff |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
c |
17 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 164
State parse_inner_ethernet (from state parse_erspan_t3)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1f |
ffff |
fe |
83 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
1 |
7c |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
11 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b5 |
b7 |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
64 |
66 |
0 |
0 |
1 |
1 |
0 |
c |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
31 |
0 |
33 |
2 |
19 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
0 |
|
Row 163
State parse_inner_ipv4 (from state parse_erspan_t3)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1f |
ffff |
fe |
8b |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
1 |
7c |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
a |
9 |
0 |
0 |
1 |
1 |
1 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
a7 |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
10 |
17 |
4 |
9 |
0 |
0 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 162
State <leaf> (from state parse_erspan_t3)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
1f |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 161
State parse_inner_ipv4 (from state parse_ipv4_in_ip)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
20 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
a |
9 |
0 |
0 |
1 |
1 |
1 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
a7 |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
10 |
17 |
4 |
9 |
0 |
0 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 160
State parse_inner_ipv6 (from state parse_ipv6_in_ip)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
21 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
f |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a5 |
1ff |
3d |
0 |
0 |
0 |
0 |
5e |
61 |
5a |
5c |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
c |
17 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 159
State parse_ipv4_option_32b//spilled (from state parse_ipv4_option_32b)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
23 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
18 |
3d |
0 |
0 |
9 |
1 |
1 |
0 |
0 |
6 |
0 |
18 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
101 |
0 |
1ff |
14 |
59 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 158
State parse_ipv4_no_options (from state parse_ipv4_fragmented_first_pkt)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
25 |
ffff |
ff |
f5 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
13 |
0 |
0 |
9 |
1 |
1 |
0 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
a6 |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
10 |
16 |
4 |
51 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 157
State parse_ipv4_option_32b (from state parse_ipv4_fragmented_first_pkt)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
25 |
ffff |
ff |
f6 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
a6 |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
10 |
16 |
4 |
51 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 156
State parse_ipv4_other (from state parse_ipv4_fragmented_first_pkt)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
25 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
a6 |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
10 |
16 |
4 |
51 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 155
State parse_ipv4_no_options (from state parse_ipv4_fragmented_other_pkt)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
26 |
ffff |
ff |
f5 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
13 |
0 |
0 |
9 |
1 |
1 |
0 |
0 |
6 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
a6 |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
10 |
16 |
4 |
51 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 154
State parse_ipv4_option_32b (from state parse_ipv4_fragmented_other_pkt)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
26 |
ffff |
ff |
f6 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
a6 |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
10 |
16 |
4 |
51 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 153
State parse_ipv4_other (from state parse_ipv4_fragmented_other_pkt)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
26 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
a6 |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
a |
2 |
0 |
0 |
1ff |
c |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
10 |
16 |
4 |
51 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
0 |
1 |
|
Row 152
State parse_ipv6//spilled (from state parse_ipv6)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
27 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
1e |
3e |
0 |
0 |
6 |
1 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1a |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1c |
0 |
1e |
14 |
10 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 151
State parse_inner_ethernet (from state parse_ethernet_in_ip)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
28 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
11 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b5 |
b7 |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
64 |
66 |
0 |
0 |
1 |
1 |
0 |
c |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
31 |
0 |
33 |
2 |
19 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
0 |
|
Row 150
State parse_arp_rarp_req (from state parse_arp_rarp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
29 |
1 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
2a |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 149
State parse_arp_rarp_res (from state parse_arp_rarp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
29 |
2 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
2b |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 148
State <leaf> (from state parse_arp_rarp)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
29 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 147
State parse_set_prio_med (from state parse_arp_rarp_req)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2a |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 146
State parse_set_prio_med (from state parse_arp_rarp_res)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2b |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 145
State parse_qinq_vlan (from state parse_qinq)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2d |
8100 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
2e |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
140 |
1ff |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
122 |
123 |
0 |
0 |
1 |
1 |
0 |
2 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
29 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
|
Row 144
State <leaf> (from state parse_qinq)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2d |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 143
State parse_mpls__it0 (from state parse_qinq_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2e |
8847 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
4 |
0 |
0 |
2 |
1 |
0 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
c7 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
59 |
70 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 142
State parse_ipv4 (from state parse_qinq_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2e |
800 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
12 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 141
State parse_ipv6 (from state parse_qinq_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2e |
86dd |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
1ff |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
c |
16 |
0 |
61 |
0 |
0 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 140
State parse_arp_rarp (from state parse_qinq_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2e |
806 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
29 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 139
State parse_set_prio_high (from state parse_qinq_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2e |
88cc |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 138
State parse_set_prio_high (from state parse_qinq_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2e |
8809 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 137
State <leaf> (from state parse_qinq_vlan)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2e |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 136
State parse_fabric_timestamp_header (from state parse_fabric_header_parse_fabric_header_cpu)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2f |
8 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
6 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
6 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
97 |
1ff |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
11 |
0 |
1ff |
2 |
21 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 135
State parse_fabric_payload_header (from state parse_fabric_header_parse_fabric_header_cpu)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
2f |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
2 |
31 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
2 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b4 |
1ff |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 134
State parse_fabric_payload_header (from state parse_fabric_timestamp_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
30 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
2 |
31 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
2 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b4 |
1ff |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 133
State parse_llc_header (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
1ff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
fe00 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
3 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
3 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
141 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
134 |
1ff |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 132
State parse_llc_header (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
5ff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
fa00 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
3 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
3 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
141 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
134 |
1ff |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 131
State parse_vlan (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
8100 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
3 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
92 |
b2 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
2 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 130
State parse_qinq (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
88a8 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
2d |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
92 |
b2 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
2 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 129
State parse_mpls__it0 (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
8847 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
4 |
0 |
0 |
2 |
1 |
0 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
c7 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
59 |
70 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 128
State parse_ipv4 (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
800 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
12 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 127
State parse_ipv6 (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
86dd |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
1ff |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
c |
16 |
0 |
61 |
0 |
0 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 126
State parse_arp_rarp (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
806 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
29 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 125
State parse_set_prio_high (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
88cc |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 124
State parse_set_prio_high (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
8809 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 123
State <leaf> (from state parse_fabric_payload_header)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
31 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 122
State <Metadata bridge>//spilled (from state <POV skip>_<Metadata bridge>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
34 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
1a |
3f |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1a |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
a0 |
0 |
99 |
9d |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
a |
c |
0 |
18 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 121
State start_e2e_mirrored (from state <Egress mirror #0 ('p4_field_list.cpu_info')>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
36 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
e |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b3 |
b6 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
63 |
65 |
0 |
0 |
1 |
1 |
0 |
c |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
30 |
0 |
32 |
2 |
39 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
0 |
|
Row 120
State start_e2e_mirrored (from state <Egress mirror #1 ('p4_field_list.e2e_mirror_info')>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
37 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
e |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b3 |
b6 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
63 |
65 |
0 |
0 |
1 |
1 |
0 |
c |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
30 |
0 |
32 |
2 |
39 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
0 |
|
Row 119
State <Ingress mirror #1 ('p4_field_list.i2e_mirror_info')>_start_i2e_mirrored (from state <POV initialization>_<Egress intrinsic metadata>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
38 |
ffff |
ff |
c9 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
3f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
17 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
1 |
1 |
0 |
b6 |
0 |
99 |
b3 |
3c |
0 |
0 |
0 |
0 |
63 |
65 |
74 |
74 |
0 |
0 |
1 |
1 |
15 |
3 |
0 |
9 |
1ff |
b |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
10 |
11 |
30 |
5 |
39 |
0 |
0 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
10 |
1 |
0 |
f |
|
Row 118
State <Egress mirror #0 ('p4_field_list.cpu_info')> (from state <POV initialization>_<Egress intrinsic metadata>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
38 |
ffff |
ff |
d8 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
3f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
9 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
95 |
0 |
90 |
93 |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
74 |
1ff |
0 |
0 |
1 |
0 |
3 |
1 |
7 |
5 |
a0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 117
State <Egress mirror #1 ('p4_field_list.e2e_mirror_info')> (from state <POV initialization>_<Egress intrinsic metadata>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
38 |
ffff |
ff |
d9 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
3f |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
7 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
1 |
1 |
0 |
1ff |
0 |
99 |
1ff |
10 |
0 |
0 |
0 |
0 |
1ff |
1ff |
74 |
74 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
10 |
3 |
0 |
0 |
|
Row 116
State <POV skip>_<Metadata bridge> (from state <POV initialization>_<Egress intrinsic metadata>)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
38 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
1 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
19 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
95 |
0 |
90 |
93 |
10 |
0 |
0 |
0 |
0 |
55 |
58 |
51 |
52 |
0 |
0 |
1 |
0 |
3 |
1 |
7 |
5 |
98 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
13 |
0 |
1ff |
15 |
11 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
a |
9 |
0 |
f |
|
Row 115
State parse_llc_header (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
1ff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
fe00 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
3 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
3 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
141 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
134 |
1ff |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 114
State parse_llc_header (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
5ff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
fa00 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
3 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
3 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
141 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
134 |
1ff |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 113
State parse_fabric_header_parse_fabric_header_cpu (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
9000 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
2f |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
96 |
0 |
91 |
94 |
3d |
0 |
0 |
0 |
0 |
1ff |
1ff |
72 |
120 |
0 |
1 |
1 |
1 |
8 |
a |
6 |
c |
a1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3d |
0 |
100 |
31 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
|
Row 112
State parse_mtel_least_int (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
9002 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 111
State parse_vlan (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
8100 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
3 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
92 |
b2 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
2 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 110
State parse_qinq (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
88a8 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
2d |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
92 |
b2 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
2 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 109
State parse_mpls__it0 (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
8847 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
4 |
0 |
0 |
2 |
1 |
0 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
c7 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
59 |
70 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3 |
0 |
0 |
|
Row 108
State parse_ipv4 (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
800 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
12 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 107
State parse_ipv6 (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
86dd |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a2 |
1ff |
3c |
0 |
0 |
0 |
0 |
5d |
60 |
59 |
5b |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
14 |
c |
16 |
0 |
61 |
0 |
0 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
1d |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
1c |
|
Row 106
State parse_arp_rarp (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
806 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
29 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
6 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 105
State parse_set_prio_high (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
88cc |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 104
State parse_set_prio_high (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
8809 |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
ffff |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 103
State <leaf> (from state start_parse_ethernet)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
39 |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 102
State parse_inner_icmp (from state parse_inner_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3a |
ffff |
ff |
3a |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
1ff |
1ff |
34 |
0 |
0 |
0 |
0 |
1ff |
1ff |
77 |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
|
Row 101
State parse_inner_tcp (from state parse_inner_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3a |
ffff |
ff |
6 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b1 |
0 |
a4 |
ac |
34 |
0 |
0 |
0 |
0 |
57 |
1ff |
77 |
54 |
0 |
0 |
1 |
0 |
6 |
4 |
0 |
2 |
1ff |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
35 |
0 |
36 |
c |
8 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
10 |
0 |
1 |
|
Row 100
State parse_inner_udp (from state parse_inner_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3a |
ffff |
ff |
11 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b1 |
0 |
a4 |
ac |
1ff |
0 |
0 |
0 |
0 |
57 |
1ff |
77 |
54 |
0 |
0 |
1 |
0 |
2 |
4 |
0 |
6 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
20 |
0 |
1 |
|
Row 99
State <leaf> (from state parse_inner_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3a |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 98
State parse_icmp (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
3a |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
14 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
1ff |
1ff |
31 |
0 |
0 |
0 |
0 |
1ff |
1ff |
77 |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
|
Row 97
State parse_tcp (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
6 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
16 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b0 |
0 |
a5 |
a7 |
31 |
0 |
0 |
0 |
0 |
5c |
1ff |
77 |
5a |
0 |
0 |
1 |
0 |
6 |
4 |
0 |
2 |
1ff |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
33 |
0 |
34 |
c |
8 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
2 |
0 |
1 |
|
Row 96
State parse_ipv4_in_ip (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
4 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 95
State parse_udp (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
11 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
8 |
17 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b0 |
0 |
a3 |
ab |
1ff |
0 |
0 |
0 |
0 |
56 |
1ff |
77 |
53 |
0 |
0 |
1 |
0 |
2 |
4 |
0 |
6 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
1 |
|
Row 94
State parse_gre (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
2f |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
1b |
3 |
0 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b0 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
56 |
71 |
0 |
0 |
1 |
1 |
0 |
2 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
71 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
|
Row 93
State parse_ipv6_in_ip (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
29 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 92
State parse_ethernet_in_ip (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
3b |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
28 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 91
State parse_set_prio_med (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
58 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 90
State parse_set_prio_med (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
59 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 89
State parse_set_prio_med (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
67 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 88
State parse_set_prio_med (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
70 |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 87
State <leaf> (from state parse_ipv6//split)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3b |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 86
State parse_inner_ipv6//split (from state parse_inner_ipv6//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3c |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
a |
3a |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
a |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a7 |
1ff |
21 |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
23 |
0 |
1ff |
6 |
2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 85
State parse_icmp (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
1 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
14 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
1ff |
0 |
1ff |
1ff |
31 |
0 |
0 |
0 |
0 |
1ff |
1ff |
77 |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
|
Row 84
State parse_tcp (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
6 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
14 |
16 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
14 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b0 |
0 |
a5 |
a7 |
31 |
0 |
0 |
0 |
0 |
5c |
1ff |
77 |
5a |
0 |
0 |
1 |
0 |
6 |
4 |
0 |
2 |
1ff |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
33 |
0 |
34 |
c |
8 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
2 |
0 |
1 |
|
Row 83
State parse_udp (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
11 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
8 |
17 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
2 |
0 |
8 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
1 |
0 |
b0 |
0 |
a3 |
ab |
1ff |
0 |
0 |
0 |
0 |
56 |
1ff |
77 |
53 |
0 |
0 |
1 |
0 |
2 |
4 |
0 |
6 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
0 |
1 |
|
Row 82
State parse_gre (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
2f |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
4 |
1b |
3 |
0 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b0 |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
56 |
71 |
0 |
0 |
1 |
1 |
0 |
2 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
71 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
|
Row 81
State parse_ipv4_in_ip (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
4 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 80
State parse_ipv6_in_ip (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
29 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 79
State parse_igmp (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
2 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
4 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
18 |
0 |
1ff |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 78
State parse_set_prio_med (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
58 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 77
State parse_set_prio_med (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
59 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 76
State parse_set_prio_med (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
67 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 75
State parse_set_prio_med (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
e000 |
ff |
70 |
1 |
1 |
1 |
1 |
mask |
ff |
1fff |
0 |
ff |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 74
State <leaf> (from state parse_ipv4_option_32b//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3d |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
1ff |
1ff |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 73
State parse_ipv6//split (from state parse_ipv6//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3e |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
a |
3b |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
a |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
a6 |
1ff |
20 |
0 |
0 |
0 |
0 |
1ff |
1ff |
1ff |
1ff |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
22 |
0 |
1ff |
6 |
2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Row 72
State start_parse_ethernet (from state <Metadata bridge>//spilled)
[ .] Raw register data
TCAM word:
|
curr_state |
lookup_16 |
lookup_8[1] |
lookup_8[0] |
ver_1 |
ver_0 |
ctr_zero |
ctr_neg |
value |
3f |
ffff |
ff |
ff |
1 |
1 |
1 |
1 |
mask |
ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Early action:
ctr_amt_idx |
nxt_state_mask |
shift_amt |
nxt_state |
lookup_offset_8[1] |
ctr_ld_src |
lookup_offset_8[0] |
ld_lookup_8[0] |
ld_lookup_16 |
ld_lookup_8[1] |
done |
lookup_offset_16 |
ctr_load |
buf_req |
0 |
ff |
e |
39 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
c |
0 |
e |
Action:
phv_8b_src_type_3 |
phv_8b_src_type_2 |
phv_8b_src_type_1 |
phv_8b_src_type_0 |
csum_addr[1] |
phv_16b_dst_2 |
phv_8b_offset_rot_imm_0 |
phv_16b_dst_0 |
phv_16b_dst_1 |
phv_32b_dst_0 |
phv_8b_offset_add_dst_1 |
phv_8b_offset_add_dst_0 |
phv_8b_offset_add_dst_3 |
phv_8b_offset_add_dst_2 |
phv_8b_dst_2 |
phv_8b_dst_3 |
phv_8b_dst_0 |
phv_8b_dst_1 |
pri_upd_en_shr |
phv_32b_src_type_1 |
dst_offset_rst |
phv_32b_src_type_0 |
phv_16b_src_1 |
phv_16b_src_0 |
phv_16b_src_3 |
phv_16b_src_2 |
phv_16b_dst_3 |
phv_32b_src_2 |
pri_upd_src |
phv_16b_offset_add_dst_3 |
phv_16b_offset_rot_imm_1 |
csum_en[1] |
phv_16b_offset_add_dst_1 |
phv_16b_offset_add_dst_0 |
dst_offset_inc |
phv_16b_offset_add_dst_2 |
csum_addr[0] |
pri_upd_type |
phv_32b_dst_1 |
phv_32b_src_3 |
phv_32b_dst_2 |
phv_32b_src_1 |
phv_32b_src_0 |
phv_32b_offset_rot_imm_1 |
phv_32b_offset_rot_imm_0 |
phv_8b_offset_rot_imm_3 |
phv_8b_offset_rot_imm_2 |
phv_16b_offset_rot_imm_0 |
phv_32b_dst_3 |
pri_upd_val_mask |
phv_16b_src_type_1 |
phv_16b_src_type_0 |
phv_8b_src_3 |
csum_en[0] |
phv_32b_offset_add_dst_3 |
phv_32b_offset_add_dst_2 |
phv_32b_offset_add_dst_1 |
phv_32b_offset_add_dst_0 |
phv_8b_src_1 |
phv_8b_src_0 |
phv_8b_offset_rot_imm_1 |
phv_8b_src_2 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
b3 |
b6 |
3c |
0 |
0 |
0 |
0 |
1ff |
1ff |
63 |
65 |
0 |
0 |
1 |
1 |
0 |
c |
0 |
0 |
1ff |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
30 |
0 |
32 |
2 |
39 |
0 |
0 |
0 |
0 |
0 |
1ff |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
7 |
6 |
0 |
0 |
|
Row 71
Unmatchable
|
Row 70
Unmatchable
|
Row 69
Unmatchable
|
Row 68
Unmatchable
|
Row 67
Unmatchable
|
Row 66
Unmatchable
|
Row 65
Unmatchable
|
Row 64
Unmatchable
|
Row 63
Unmatchable
|
Row 62
Unmatchable
|
Row 61
Unmatchable
|
Row 60
Unmatchable
|
Row 59
Unmatchable
|
Row 58
Unmatchable
|
Row 57
Unmatchable
|
Row 56
Unmatchable
|
Row 55
Unmatchable
|
Row 54
Unmatchable
|
Row 53
Unmatchable
|
Row 52
Unmatchable
|
Row 51
Unmatchable
|
Row 50
Unmatchable
|
Row 49
Unmatchable
|
Row 48
Unmatchable
|
Row 47
Unmatchable
|
Row 46
Unmatchable
|
Row 45
Unmatchable
|
Row 44
Unmatchable
|
Row 43
Unmatchable
|
Row 42
Unmatchable
|
Row 41
Unmatchable
|
Row 40
Unmatchable
|
Row 39
Unmatchable
|
Row 38
Unmatchable
|
Row 37
Unmatchable
|
Row 36
Unmatchable
|
Row 35
Unmatchable
|
Row 34
Unmatchable
|
Row 33
Unmatchable
|
Row 32
Unmatchable
|
Row 31
Unmatchable
|
Row 30
Unmatchable
|
Row 29
Unmatchable
|
Row 28
Unmatchable
|
Row 27
Unmatchable
|
Row 26
Unmatchable
|
Row 25
Unmatchable
|
Row 24
Unmatchable
|
Row 23
Unmatchable
|
Row 22
Unmatchable
|
Row 21
Unmatchable
|
Row 20
Unmatchable
|
Row 19
Unmatchable
|
Row 18
Unmatchable
|
Row 17
Unmatchable
|
Row 16
Unmatchable
|
Row 15
Unmatchable
|
Row 14
Unmatchable
|
Row 13
Unmatchable
|
Row 12
Unmatchable
|
Row 11
Unmatchable
|
Row 10
Unmatchable
|
Row 9
Unmatchable
|
Row 8
Unmatchable
|
Row 7
Unmatchable
|
Row 6
Unmatchable
|
Row 5
Unmatchable
|
Row 4
Unmatchable
|
Row 3
Unmatchable
|
Row 2
Unmatchable
|
Row 1
Unmatchable
|
Row 0
Unmatchable
|
Matchable row occupancy: 184/256 (71.88%)
|